Abstract:

This presentation explores communication challenges in 2.5D chiplet systems, highlighting interconnectivity and bandwidth demands. Achieving interconnectivity involves microbumps connecting chiplets to the interposer, utilizing an electrical network with a deadlock-free, fault-tolerant routing algorithm. However, electrical interposer networks encounter challenges meeting high bandwidth and low latency demands for inter-chiplet communication. On-chip optical communication emerges as a solution, providing low latency and high bandwidth. Nevertheless, optical communication introduces power consumption challenges, leading to the development of a reconfigurable, power-efficient silicon photonic interposer network. Leveraging these innovations, 2.5D chiplet systems advance in terms of cost-effectiveness, modular designs, and enhanced energy efficiency, particularly in machine learning accelerators.